在英特爾以 20 億美元競購業(yè)界領(lǐng)先的 RISC-V 設(shè)計(jì)公司SiFive 之后，開源 RISC-V 指令集架構(gòu)正獲得更多主流關(guān)注。不幸的是，RISC-V 長期以來一直被降級為較小的芯片和微控制器，這限制了它的吸引力。然而，隨著監(jiān)管 RISC-V 指令集架構(gòu) （ISA） 開發(fā)的組織 RISC-V International宣布計(jì)劃將該架構(gòu)擴(kuò)展到高性能計(jì)算、人工智能和超級計(jì)算應(yīng)用程序，這種情況應(yīng)該很快就會改變。
RISC-V 開源 ISA 于 2016 年首次推出，但最初的內(nèi)核僅適用于微控制器和一些基本的片上系統(tǒng)設(shè)計(jì)。然而，經(jīng)過幾年的發(fā)展，眾多芯片開發(fā)商（如阿里巴巴）已經(jīng)針對云數(shù)據(jù)中心、AI 工作負(fù)載（如 Jim Keller 主導(dǎo)的 Tenstorrent）和高級存儲應(yīng)用（如希捷、西部數(shù)據(jù)）創(chuàng)建了設(shè)計(jì)。
這意味著開發(fā)人員對高性能RISC-V芯片很感興趣。但是，為了促進(jìn)邊緣、HPC 和超級計(jì)算應(yīng)用程序采用 RISC-V ISA，該行業(yè)需要更強(qiáng)大的硬件和軟件生態(tài)系統(tǒng)（以及與傳統(tǒng)應(yīng)用程序和基準(zhǔn)測試的兼容性）。這就是用于HPC的RISC-V SIG發(fā)揮作用的地方。
目前，RISC-V SIG-HPC的郵件列表中有141名成員，研究、學(xué)術(shù)和芯片行業(yè)有 10 名活躍成員。不斷壯大的SIG的關(guān)鍵任務(wù)是提出各種新的HPC特定指令和擴(kuò)展，并與其他技術(shù)小組合作，確保為不斷發(fā)展的ISA考慮HPC要求。作為這項(xiàng)任務(wù)的一部分，SIG需要定義AI/HPC/邊緣要求，并繪制一條特征和能力路徑，以達(dá)到 RISC-V 與 Arm、x86 和其他架構(gòu)競爭的程度。
RISC-V SIG-HPC 也有短期目標(biāo)。2021年，該集團(tuán)將專注于HPC軟件生態(tài)系統(tǒng)。首先，該小組計(jì)劃尋找開箱即用的可以與RISC-V ISA一起使用的開源軟件（基準(zhǔn)測試、庫和實(shí)際程序）。這個(gè)過程被設(shè)置為自動化。首批調(diào)查將針對 GROMACS、Quantum ESPRESSO和CP2K等應(yīng)用；FFT、BLAS、GCC 和LLVM等庫；以及HPL和HPCG等基準(zhǔn)測試。
RISC-V SIG-HPC將在生態(tài)系統(tǒng)固化后制定更詳細(xì)的路線圖。RISC-V SIG的長期目標(biāo)是構(gòu)建一個(gè)開源的硬件和軟件生態(tài)系統(tǒng)，既可以滿足對性能要求高的新興應(yīng)用程序，又可以滿足傳統(tǒng)需求。
這需要多少年？只有時(shí)間會證明一切，但來自英特爾等大公司的行業(yè)支持肯定有助于加快這一時(shí)間表。
RISC-V官方原文：
RISC-V SIG-HPC Enabling RISC-V in HPC, Supercomputers to the Edge, and Emerging AI/ML/DL HPC WorkloadsRISC-V was first deployed as a microcontroller or embedded processor. However, in the future, the RISC-V ISA can also power the most powerful computers as processors and accelerators. In order to do that, the ISA must have features and an ecosystem to support HPC and these features are different from what is defined as an embedded system, where the RISC-V ISA first got traction.
The RISC-V Special Interest Group on High Performance Computing （SIG-HPC） was formed to address the requirements of the HPC community and align the RISC-V ISA. The SIG is a global committee that works on enabling HPC with the RISC-V ISA and its goal is to enable RISC-V in a broader set of new software and hardware opportunities in the high performance computing space, supercomputers to the edge, and the software ecosystem required to run legacy and emerging （AI/ML/DL） HPC workloads. First, the SIG defined HPC to provide overall group scope and define the target markets, users, and applications. With this definition and scope, the interests of the SIG-HPC were rank ordered to provide high impact results, from discovery and gap analysis to implementation. In order to accomplish this, two things need to take place: 1） Plot a path to becoming competitive and 2） Extend that path to lead the community with new features and capabilities.
A broad definition of HPC from the SIG and some related commentary:
“A computer system designed to execute applications that would take days/years/centuries on a desktop/mobile device, in seconds/minutes or require weeks or months to run, even at large scale.”
Various technologies are used to achieve this speedup. Over time, newer technologies and applications will be developed with newer access methods and implementation methodologies. Some applications may consume the entire computer system, while in other scenarios the computer system may be partitioned to run many applications.
In HPC, one can expect very large main memory capacities and very large online datasets. These capabilities will be used to increase the fidelity of the answer and/or some applications will be required to provide answers in a real-time transaction environment. Access may be limited to a particular organization or globally accessible in a cloud environment.
As the HPC definition suggests, HPC is everywhere. The basic algorithms and kernels power a wide range of computations. It starts in the traditional space of supercomputers used for weather forecasting, computational fluid dynamics, to material science, and protein folding, in both research and industrial applications. We even see HPC in the cloud.
The SIG-HPC aims to enable all of those workloads and more. As a result, there are 141 members on the mailing list and 10 active research, academia, and industrial members from a wide range of organizations and these are growing exponentially. The group is united in making RISC-V an option in HPC. It also works with other technical groups in RISC-V to make sure HPC requirements are kept in mind for the evolving ISA.
For 2021, SIG-HPC's goals are to start new initiatives, such as mapping the HPC software ecosystem to RISC-V. This involves automation to discover which open source software, from libraries to benchmarks and applications, work out-of-the-box on the RISC-V ISA. SIG-HPC is starting with the most common libraries like FFT, BLAS, and using GCC and LLVM to compile the codes. The same automation is being applied to benchmarks like HPL and HPCG as well as applications like GROMACS, Quantum ESPRESSO and CP2K. The list is growing! Based on this work, efforts can be targeted to increase library to application coverage by the RISC-V software ecosystem.
Overall, SIG-HPC's vision is that of a future where the entire HPC system can be based on open source components. Today's technology trends require specialization to meet the power and performance workload targets. This enables hardware-software co-design, which is a natural fit for open systems, enabling more research and development. The next major milestone for SIG-HPC is to map the HPC ecosystem and develop an associated roadmap. This is where you can get involved!
John D. Davis, Ph.D.
SIG-HPC Chair
