中圖分類號：TN432 文獻(xiàn)標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.234437
中文引用格式： 趙達(dá)，沈丹丹，王亞軍，等. 基于先進(jìn)CMOS工藝的多通道Gbps LVDS接收器[J]. 電子技術(shù)應(yīng)用，2024，50(5)：24-29.
英文引用格式： Zhao Da，Shen Dandan，Wang Yajun，et al. Multi channels Gbps LVDS receiver based on advanced CMOS[J]. Application of Electronic Technique，2024，50(5)：24-29.

Multi channels Gbps LVDS receiver based on advanced CMOS

Abstract： When integrating multi-channel high-speed ADC (Analog-to-Digital Converter) with LVDS (Low Voltage Differential Signal) interface in SIP (System In a Package) system, it is faced with the problem of clock-to-data skew, data-to-data skew, accumulated clock jitter and so on caused by different LVDS channel with different delays. Therefore, a multi-channel LVDS receiver was designed in this paper which can adaptively adjust the skew of each LVDS channel. The receiver uses data clock recovery technology to generate eight multi-phase sampling clocks, combining with ADC test mode to confirm the sampling phase of each channel, the delay of each channel can be automatically adjusted, aiming to align the sampling phase of channels and ensure the data correct. Finally, the receiver was designed, simulated, and realized based on advanced CMOS technology. The results of simulation and chip test show that the receiver can automatically adjust the delay of each channel to align the sampling phase, the maximum range of sampling phase adjustment is ± 3 bit, and the signal-to-noise ratio is greater than 65 dB, which meets the design requirements and application requirements.

Key words : analog-to-digital converter（ADC）；multi-channels LVDS；phase locked loop；clock data recover