中圖分類號： TN432
文獻標識碼： A
DOI：10.16157/j.issn.0258-7998.211378
中文引用格式： 楊德旺，張春華，郭春炳. 一種超低輸入共模電壓的動態(tài)比較器電路設(shè)計[J].電子技術(shù)應(yīng)用，2021，47(10)：48-52.
英文引用格式： Yang Dewang，Zhang Chunhua，Guo Chunbing. Design of a dynamic comparator circuit for ultra-low input common-mode voltage[J]. Application of Electronic Technique，2021，47(10)：48-52.

Design of a dynamic comparator circuit for ultra-low input common-mode voltage

Abstract： In order to adapt to the application scenarios of low power consumption in the Internet of Things, and meet the requirements of low power supply and low input common-mode voltage, this paper proposes a dynamic comparator, with dual-positive feedback loop, suitable for ultra-low input common-mode voltage. The comparator uses a timing switch to control the input and output, which solves the problem that the traditional dynamic comparator cannot work properly when the input voltage is lower than the threshold voltage, and increases the input dynamic range. Only two MOS devices are stacked in series between the power supply and the ground, which reduces the minimum power supply voltage. Two positive feedback loops are introduced to improve the resolution. TSMC 180 nm CMOS process is used to design and verify the proposed comparator. The simulation results show that the lowest common mode voltage of the proposed comparator is 51 mV when the power supply voltage is 900 mV and the differential mode voltage is 1 mV, which is 374 mV and 264 mV lower than the traditional StrongARM and DoubleTail dynamic comparators, respectively. When the input common-mode voltage is lower than the threshold voltage, it achieves best delay among three topologies at moderate power consumption.

Key words : dynamic comparator；low input common-mode voltage；low power comparator