| Virtex-5學(xué)習(xí)資料 | |
| 所屬分類：教程|講義 | |
| 上傳者：nuanyangyang | |
| 文檔大小：678 K | |
| 標(biāo)簽： FPGA | |
| 所需積分：0分積分不夠怎么辦？ | |
| 文檔介紹：The V5 already provides enhanced memory in the form of both distributed RAM and Block RAM Memory interfaces provide access to external memory: More memory than available in the FPGA Access to non-volatile memory V5's I/O's are capable of 710MHz single ended communications DRAM speeds double every 4 years V5's I/O capable of many different voltage standards New features supporting the faster memory interfaces Adaptive IDELAY, ODELAY, faster fabric (LUT6), less jitter (PLL) Dedicated error correction circuitry Use MIG | |
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